FPGA hello world – Led blink – Part II

In this post I’ll show you how to simulate our hello world design.
In ISE, in Design tab, select View Simulation as in the image below

¬† Now we “compile” our design as usual. First we select in Hierarchy our helloworld entity and click first in Behavioral Check Syntax and then Simulate Behavioral Model.

After click in Simulate, a new program will be launch – ISim.We’ll have all signals defined in our design there.

We select all signals and we add them to wave window. We can drag and drop them or right clicking all selected signals and selection Add to wave window.
We need to create our clock signal by right-clicking in clk signal and selecting Force Clock. In our case 50MHz has a 20ns period. We set our updown to 0 first and then to 1 to see what happens. Here I also changed blink_freq to 1000000 to be able to show you the results (1 Hz is an eternity for our FPGA). Click in run and that’s it!

We can see that we’re decreasing our led value when updown = 0 and increasing when updown = 1. The updown value changes in the blue cursor.

Next post, I’ll show how to configurate our FPGA and finally see our leds blink!


Marcelo Jo

Marcelo Jo is an electronics engineer with 10+ years of experience in embedded system, postgraduate in computer networks and masters student in computer vision at Universit√© Laval in Canada. He shares his knowledge in this blog when he is not enjoying his wonderful family – wife and 3 kids. Live couldn’t be better.


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